1. Field of the Invention
The present invention relates to a scan path type circuit for facilitating a functional test on a RAM (random access memory) incorporated into a chip.
2. Description of the Related Art
In a functional test on RAM, after a test pattern such as a check board pattern or a marching pattern is written into the RAM, storage contents are read out to compare with corresponding expected values, and thereby fault detection is performed. For this test, a test facilitation circuit is incorporated in an integrated circuit including a RAM.
FIG. 19 shows a prior art test facilitation circuit of a scan path type provided for a RAM 10.
This is a wrapper circuit surrounding the RAM 10 and includes holding and selecting circuits 20, 30, 40 and 50 provided for the data inputs RAM.DI, write enable input RAM.*WE, address inputs RAM.AD and data outputs RAM.DO, respectively, of the RAM 10, wherein xe2x80x9cRAM.xe2x80x9d denotes an input or output of the RAM 10. A circuit block 60 constituted of the RAM 10 and the test facilitation circuit is incorporated into an integrated circuit together with other logic circuits, and the inputs and outputs of the circuit block 60 is connected to a logic circuit or an I/O circuit in the neighborhood thereof.
For example, in the holding and selecting circuit 30, either an interconnecting line 31 or the output Q of a scan flip-flop 32 is selected by a selector 33 in accordance with the signal of a local test mode (RAM test mode) input BLK.LTM, and the selected signal on the interconnecting line 31 or the output of the scan flip-flop 32 is provided to both the write enable input RAM.*WE and the data input D of the scan flip-flop 32, where xe2x80x9cBLK.xe2x80x9d denotes an input or output of the circuit block 60.
The holding and selecting circuit 20 includes, as shown in FIG. 20, holding and selecting circuits 200 to 20N for respective data inputs RAM.DI0 to D1N. Each of the holding and selecting circuits 200 to 20N has the same configuration as that of the holding and selecting circuit 30 of FIG. 19. In FIG. 19, for simplification, data inputs DI0 to DIN having an (N+1) bit width of FIG. 20 are represented by data inputs DI, interconnecting lines 210 to 21N of FIG. 20 are represented by an interconnecting line 21, scan flip-flops 220 to 22N of FIG. 20 are represented by scan flip-flops 22 and selectors 230 to 23N of FIG. 20 are represented by selectors 23. This simplification applies to the holding and selecting circuits 40 and 50 in a similar manner.
All the scan flip-flops in the circuit block 60 have the same configuration as each other and FIG. 21 shows an example of the scan flip-flop 220.
The configuration of the scan flip-flop 220 is such that a selector 2203 for selecting either the scan in terminal SI or the data input D of the scan flip-flop 220 when a scan enable input SE is high or low, respectively, to provide it to the input of a master-slave D flip-flop including a master latch circuit 2201 and a slave latch circuit 2202. The selector 2203 has the same configuration as each of the selectors in the circuit block 60. Each selector is constituted of 4 transistors, while the scan flip-flop 220 is constituted of 32 transistors and the on-chip occupancy area thereof is 8 times that of each selector. In FIG. 21, each of TG0 to TG5 is a transfer gate constituted of a PMOS transistor and an NMOS transistor in parallel connection, and each of INV0 to INV9 is a CMOS inverter consisted of a PMOS transistor and an NMOS transistor in serial connection. In the scan flip-flop 220, the logical value of the output Q is equal to that of the scan out SO.
The scan flip-flops 22, 32, 42, and 52 of the respective holding and selecting circuits 20, 30, 40 and 50 are cascaded in regard to respective scan in SI and scan out SO to constitute a scan register. By serially providing test data for the data inputs RAM.DI, the write enable input RAM.*WE and the address inputs RAM.AD to the scan register from the scan in BLK.GSI, a functional test can be carried out on the RAM 10 independently of a state of a logic circuit in the neighborhood of the circuit block 60. That is, it is possible to perform fault detection by writing an arbitrary test pattern into the RAM 10 by repeating the operations of both serially transferring the test data to the scan register and writing the test data into the RAM 10; reading out the storage contents through the data outputs RAM.DO to capture them into the scan flip-flops 52 of the holding and selecting circuit 50; and serially reading out the captured data through the scan out BLK.GSO to compare them with expected values.
However, since the test data has to be serially transferred to the scan register, a test time increases with increase in bit width of the data input RAM.DI. Further, since especially the number of scan flip-flops increases with the increase in bit width, the on-chip occupancy area of the test facilitating circuit increases. A circuit scale becomes larger due to multifunctionarization of an integrated circuit and the test facilitating circuit is not used in a normal operation, therefore the on-chip occupancy area of the test facilitating circuit is preferably to be the smallest possible.
On the other hand, there are available as typical test patterns a check board pattern and a marching pattern. In a case where these test patterns are used, such test data as all bits being xe2x80x9c0sxe2x80x9d, all bits being xe2x80x9c1sxe2x80x9d, or alternate xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are repeatedly held in the scan flip-flops 22; therefore, it is conceivable to simplify the holding and selecting circuit 20.
However, since the scan flip-flops 22 are also part of a scan path type test facilitation circuit for a whole integrated circuit including the circuit block 60 and a logic circuit outside the circuit block 60, the scan flip-flops 22 itself have to capture signals to the data inputs RAM.DI from the logic circuit outside the circuit block 60, having disabled simplification of the configuration of the holding and selecting circuit 20 in the prior art.
Note that although a scan path is formed outside RAM 10 in the circuit of FIG. 19, in a case where flip-flops in RAM 10 are exchanged for scan flip-flops to constitute a scan path, the scan path cannot be simplified to reduce test time. Further, in a case where design data for the RAM 10 is provided from another maker, details in the RAM 10 are not clear, and therefore it is impossible that flip-flops in the RAM 10 are exchanged for scan flip-flops to constitute a scan path.
Accordingly, it is an object of the present invention to provide a RAM functional test facilitation circuit capable of reducing its scale to decrease an on-chip occupancy area and to shorten a test time.
In one aspect of the present invention, there is provided a circuit for facilitating a functional test on a RAM (10A), wherein the outputs of a plurality of first selectors (230 to 23N) are connected to the respective data inputs (DI0 to DIN) of the RAM, the first inputs of a plurality of second selectors (540 to 54N) are connected to the respective data outputs (DO0 to DON) of the RAM, the second inputs of the second selectors are connected to the respective data inputs (DI0 to DIN) of the RAM, and the outputs of the second selectors are connected to the respective data inputs of the second scan flip-flops (520 to 52N).
When a test mode signal is inactive, the first inputs of the first selectors are selected to provide data to the data inputs of the RAM, and the outputs of the first selectors are selected by the second selectors to provide the data to the data inputs of the second scan flip-flops.
With this, in a functional test on a logic circuit, since outputs of the logic circuit provided to the RAM can be captured into the second scan flip-flops, no necessity arises for capturing the outputs by first scan flip-flops (22 of FIG. 19) to be connected to the second inputs of the first selectors (230 to 23N), and therefore the first scan flip-flop (220) can be exclusively used for the RAM functional test. Hence for a simple pattern such as a marching pattern, an output of one first scan flip-flop has only to be selected by the plurality of first selectors to provide the selected data to the RAM. Since the number of transistors in a scan flip-flop is, for example, xe2x85x9 times that of a selector, according to the above aspect, the circuit scale of the RAM functional test facilitation circuit can be reduced to thereby decrease an on-chip occupancy area thereof.
Further, since the number of first scan flip-flops can be greatly reduced, the bit length of a scan register is shortened to decrease the number of necessary shift clock pulses, thereby reducing a test time.
In other aspect of the present invention, the contents of the scan register to be provided to the data and address inputs of the RAM are maintained in a read and write test operation on the RAM for the same address, the test time can be further reduced.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.